Books written by Ricardo Reis

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  VLSI-SoC: Technologies for Systems Integration: 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil,...

  4.1 Heterogeneous Hardware Integration Silicon integration technology will not reach the end of affordable fabrication on planar ... An important impact on computing and communication will happen with the optoelectronics integration.

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  VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT,...

  Pedram, A., Richardson, S., Horowitz, M., Galal, S., Kvatinsky, S.: Dark memory and accelerator-rich system optimization in the dark silicon era. IEEE Des. Test 34(2), 39–50 (2017) 2. Hamdioui, S., et al.: Memristor for computing: myth ...

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  Design of Systems on a Chip: Design and Test

  Multi-stage conventional System-on-Board Test versus single stage System-on-Chip Test SOC. ... SoB Verification SoB Manufacturing SoB Test Core Design Core Verification SoC Design SoC Verification SoC Manufacturing SoC Test 222 CHAPTER 11.

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  VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms: 26th IFIP WG 10.5/IEEE International Conference on Very...

  Yamashita, K., Joo, S.-K., Li, J., Zhang, P., Liu, C.-C.: Analysis, control, and economic impact assessment of major ... IEEE (2012) North American Synchrophasor Initiative (NASPI): Time synchronization in the electric power system ...

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  Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS

  This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power.

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  Protecting Chips Against Hold Time Violations Due to Variability

  ... holding the signal stable until the next rising (falling) edge. FFs are usually used to store data during a short or long time and also to store data only during a ... Hold Time Violations 3.1 Flip-Flop Timing Metrics 3.1.1 Setup Time.

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  And Yet it Moves: Inflation and the Great Recession

  But, like Galileo Galilei told his contemporaries who thought the Earth was immovable, "Eppur si muove" ("and yet it moves").

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  VLSI-SoC: Design Methodologies for SoC and SiP: 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008,...

  16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island ... microfluidic device able to trap functionalized micro beads. As it will be shown below, this technology combines standard ...

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  VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC...

  ... designer's guide to asynchronous VLSI. Cambridge University Press (2010) 2. Smith, S.C., Di, J.: Designing asynchronous circuits using NULL Convention Logic (NCL). In: Synthesis Lectures on Digital Circuits and Systems, vol. 4/1. Morgan ...

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  VLSI-SoC: Forward-Looking Trends in IC and Systems Design: 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC...

  ... forwarding of the incoming packets. Figure10shows the second migration protocol. The initial situation is same as before: 2 tasks are communicating, task 1 sending to task 2 (step 0). When the NPU decides to trigger a migration, it does ...

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  Soft Error Reliability Using Virtual Platforms: Early Evaluation of Multicore Systems

  ... soft errors results in memory elements incorrect operation. At architecture level (e.g., program counter, pipeline registers, register file, arithmetic, and logic unit), an erroneous bit can be ... Soft Errors 2.2.3 Soft Error Metrics.

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  VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability: 24th IFIP WG 10.5/IEEE International Conference on Very Large...

  This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016.